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| MM74HC4060 14 Stage Binary Counter August 1984 Revised February 1999 MM74HC4060 14 Stage Binary Counter General Description The MM74HC4060 is a high speed binary ripple carry counter. These counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS. The MM74HC4060 is a 14-stage counter, which device increments on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. The MM74HC4060 also has two additional inputs to enable easy connection of either an RC or crystal oscillator. This device is pin equivalent to the CD4060. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground. Features s Typical propagation delay: 16 ns s Wide operating voltage range: 2-6V s Low input current: 1 A maximum s Low quiescent current: 80 A maximum (74 Series) s Output drive capability: 10 LS-TTL loads Ordering Code: Order Number MM74HC4060M MM74HC4060SJ MM74HC4060MTC MM74HC4060N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (c) 1999 Fairchild Semiconductor Corporation DS005354.prf www.fairchildsemi.com MM74HC4060 Logic Diagram www.fairchildsemi.com 2 MM74HC4060 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 -40 VCC +85 V C 2 Max 6 Units V Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating: plastic "N" package: -12 mW/C from 65C to 85C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Voltage (Not Applicable to Pins 9 & 10) VIL Maximum LOW Level Input Voltage (Not Applicable to Pins 9 & 10) VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 3.98 5.48 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 3.84 5.34 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 3.7 5.2 Units V V V V V V V V V V V V V Conditions Except Pins 9 & 10 Pins 9 & 10 VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VIN = VIH or VIL |IOUT| = 0.4 mA |IOUT| = 0.52 mA VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V 0 0 0 0.2 0.2 0.1 0.1 0.1 0.26 0.26 0.26 0.26 6.0V 6.0V 0.1 8.0 0.1 0.1 0.1 0.33 0.33 0.33 0.33 1.0 80 0.1 0.1 0.1 0.4 0.4 0.4 0.4 1.0 160 V V V V V V V A A 4.5V 6.0V Except Pins 9 & 10 Pins 9 & 10 IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VIN = VIH or VIL |IOUT| = 0.4 mA |IOUT| = 0.52 mA VIN = VCC or GND VIN = VCCor GND IOUT = 0 A 4.5V 6.0V Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at V CC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC4060 AC Electrical Characteristics VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tREM tW Parameter Maximum Clock Frequency Maximum Propagation Delay to Q4 Maximum Propagation Delay to any Q Minimum Reset Removal Time Minimum Pulse Width 10 16 ns 10 20 ns 16 40 ns (Note 5) 40 Conditions Typ Guaranteed Limit 30 20 Units MHz ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock to Q4 tPHL Maximum Propagation Delay Reset to any Q tPHL, tPLH Maximum Propagation Delay Between Stages Qn to Qn+1 tREM Minimum Reset Removal Time tW Minimum Pulse Width Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V tr, tf Maximum Input Rise and Fall Time tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 6) Maximum Input Capacitance Note 5: Typical Propagation delay time to any output can be calculated using: tP = 17+12(N-1) ns; where N is the number of the output, QW, at VCC = 5V. Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. TA = 25C Typ 6 30 35 120 42 35 72 24 20 380 76 65 240 48 41 125 25 21 100 20 17 80 16 14 1000 500 400 30 10 9 55 5 10 75 15 13 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 5 24 28 475 95 81 302 60 51 156 31 26 125 25 21 100 20 17 1000 500 400 95 19 16 4 20 24 171 114 97 358 72 61 188 38 31 150 30 25 120 24 20 1000 500 400 110 22 19 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V (per package) 10 10 pF www.fairchildsemi.com 4 MM74HC4060 Timing Diagram 5 www.fairchildsemi.com MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com MM74HC4060 14 Stage Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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